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Preparing the Stage for 6G: A Fast and Compact Transceiver for Sub-THz Frequencies

New transceiver design capable of both transmission and reception at frequencies over 100 GHz and at 112 Gb/s data rate could pave the way to 6G technologies, as reported by scientists at Tokyo Tech. By effectively suppressing the self-interference caused by the transmission signal leaking into the receiver, the proposed architecture reaches unprecedented data rates while maintaining a surprisingly compact size.
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Novel Architecture Can Reduce Noise-Induced Jitters in Digital Technology

Jitters are a common shortcoming of modern electronic devices using a high-frequency digital signal. While oversampling phase-locked loops (OSPLLs) can expand the loop bandwidth, effectively reducing jitter, conventional OSPLLs suffer from high jitter in noisy signal peak areas. Tokyo Tech researchers have instead suggested and demonstrated a non-uniform OSPLL that can efficiently suppress jitter through adaptive loop gain calibration. This novel architecture leads to more economical and power-efficient devices than conventional OSPLLs.
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ISSCC 2023, 6 papers will be presented

Publication in ISSCC 2023. Regular Session Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration” Dongwon You, et al., “A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler” Xi Fu, et al., “A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low Earth Orbit Small Satellite Constellation” Plenary Talk Prof. Matsuzawa, “Shape the World With Mixed-Signal Integrated Circuits – Past, Present, and Future” Chun Wang and Dingxin Xu will present their work in Student Research Preview.
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